A. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to the improvement of a method for manufacturing an insulated gate semiconductor device having a trench gate structure.
B. Description of the Related Art
With the development of a technique for reducing the power consumption of power conversion apparatuses, there are growing expectations for a technique for reducing the power consumption of a power device which plays a key role in the power conversion apparatus. For example, among various types of power devices, an insulated gate bipolar transistor (IGBT) generally has been used which can reduce an on-voltage using a conductivity modulation effect and whose gate is easily controlled for voltage driving. FIG. 24 illustrates an example of the structure of the IGBT. In FIG. 24, for ease of understanding, a portion of hatching indicating a cross section is omitted. In a planar gate IGBT 100 illustrated in the cross-sectional view of FIG. 24(a), a gate electrode 101a is provided along the surface of a wafer to form a planar gate structure. In a trench gate IGBT 200 illustrated in the cross-sectional view of FIG. 24(b), a gate electrode 203 is provided in a trench 201, which vertically extends from a stripe-shaped plane pattern on the surface of a wafer in a depth direction, with an oxide film 202 interposed therebetween, to form a trench gate structure. In the trench gate IGBT 200, an n channel (not illustrated) is formed along a p-type base region 204 which is provided on both side walls of the trench 201. I.e., the n channel is vertically formed in the surface of the substrate. Therefore, it is easy to reduce the opening width of the trench and the gap between the trenches. As a result, it is easy to increase channel density, as compared to the planar gate IGBT. In addition, it is possible to increase the density of the channels and to reduce the on-voltage. Therefore, in recent years, the application of the trench gate IGBT has increased.
For the trench gate structure which can increase channel density and reduce the on-voltage, a drawing of a trench gate structure is disclosed in which a gate electrode film formed on the inner surface of a trench is divided at the bottom (JP 2009-200103 A (FIG. 1 and paragraph 0024)). In addition, JP 2009-200103 A discloses a gate electrode division method in which a polysilicon film that is uniformly formed in the trench is etched back by anisotropic etching. U.S. Pat. No. 6,815,769 (FIG. 1) discloses a structure in which a polysilicon layer filled in a trench is divided at the bottom, only the polysilicon layer provided on a side wall close to an n+ emitter region and a p-type base region (active mesa region) is divided as a gate electrode, and the polysilicon layer close to a floating mesa region is not connected to the gate electrode, but is connected to an emitter electrode. In addition, U.S. Pat. No. 6,815,769 discloses a method for dividing the polysilicon layer. I.e., a polysilicon layer which is thick enough not to fill up the trench is formed. With the polysilicon layer remaining on the surface of the substrate, the polysilicon layer at the bottom of the trench is cut, using the oxide film as a mask. The gap between the polysilicon layers in the trench is filled with, for example, an oxide film and the polysilicon layers on both side walls are insulated from each other. Then, a drawing portion for the polysilicon layer on the surface of the substrate is formed.
FIGS. 25 to 34 are cross-sectional views sequentially illustrating the steps of a main process for manufacturing the trench gate IGBT according to the related art. As illustrated in FIG. 25, a trench 302 is formed from the surface of a silicon substrate 301 in a vertical direction by anisotropic plasma etching using, for example, the known technique of reactive ion etching (RIE). When the trench 302 is formed in the surface of the silicon substrate 301, an active mesa region 305 and a floating mesa region 306, which are partitioned by the trench 2, are formed. Then, as illustrated in FIG. 26, a gate oxide film 303a is formed in the trench 302.
As illustrated in FIG. 27, a doped polysilicon layer 304 which is thick enough not to fill up the trench 302 is formed in the trench 302 by, for example, a chemical vapor deposition (CVD) method. For example, the doped polysilicon layer 304 with a thickness of about 0.5 μm is formed in the trench with a width of 2 μm.
The doped polysilicon layer 304 is etched back by anisotropic etching so that portions of the doped polysilicon layer 304 on the surface of the silicon substrate 301 and in the bottom of the trench 302 are removed and portions of the doped polysilicon layer 304 on both side walls of the trench 2 remain, as illustrated in FIG. 28. In this process, the doped polysilicon layer 304 which is formed on the inner wall surface of the trench 302 is divided into two doped polysilicon electrodes 304a and 304b which are arranged on the side wall of the trench 302 in the width direction so as face each other with a gap therebetween. Then, as illustrated in FIG. 29, the gate oxide film 303a on the surface of the silicon substrate 301 is selectively removed by, for example, a chemical mechanical polishing (CMP) method.
Boron (B) ions are implanted into the surface of the silicon substrate 301, using a photoresist 314a formed by photolithography as a mask, in order to form a p-type base region 307 in a mesa-shaped portion of the silicon substrate between adjacent trenches 302, as illustrated in FIG. 30. The photoresist 314a is removed and a heat treatment for activating the implanted boron ions is performed to form the p-type base region 307 (see FIG. 31).
Phosphorous (P) ions are implanted into the surface of the silicon substrate 301, using a photoresist 314b formed by photolithography as a mask, in order to form an n+ emitter region 308, as illustrated in FIG. 31. The photoresist 314b is removed and a heat treatment for activating the implanted phosphorous ions is performed to form the n+ emitter region 308, as illustrated in FIG. 32.
As such, in the trench gate IGBT manufacturing method according to the related art, as illustrated in FIG. 32, the p-type base region 307 and the n+ emitter region 308 are formed in the mesa-shaped portion of the silicon substrate between adjacent trenches 302 by two ion implantation processes. In the two ion implantation processes, the trench 302 is filled with the resist (photoresists 314a and 314b) in order to prevent the implantation of ions into the bottom of the trench 302 where the gate oxide film 303a is exposed.
As illustrated in FIG. 33, the inside of the trench 2, i.e., the gap between two doped polysilicon electrodes, is filled with an oxide film 303c with high embedability, such as a high temperature oxide film (HTO) or a tetraethoxysilane (TEOS) film.
Then, as illustrated in FIG. 34, the oxide film 303c on the p-type base region 307 and the n+ emitter region 308 is selectively removed and opened and the p-type base region 307 and the n+ emitter region 308 come into contact with an emitter electrode 310. As a result, as illustrated in FIG. 34, a trench gate structure is formed in which the doped polysilicon layer 304 is divided into the doped polysilicon electrode 304a close to the active mesa region 305 and the doped polysilicon electrode 304b close to the floating mesa region 306 which are provided on both side walls of the trench 302, with the gate oxide film 303a interposed therebetween.
However, as described above, in the trench gate IGBT manufacturing method according to the related art, in FIGS. 30 and 31 illustrating the trench gate structure manufacturing process, a photolithography process is performed in order to form the p-type base region 307 and the n+ emitter region 308 in predetermined regions of the surface of the silicon substrate 301 using selective ion implantation. At that time, the photoresists 314a and 314b get into a concave portion of the trench 302 with a small width. It is necessary to remove the photoresists 314a and 314b in the trench 302 after ion implantation. However, since the trench 302 has a small width of about 2 μm, it is difficult to completely remove the hardened photoresists 314a and 314b. The remaining photoresists 314a and 314b become a contamination source and is one of the causes of low yield.